MIC59P50BV TR【PDF 1/5 页】IC DRVR LATCH 8BIT PAR IN 28PLCC

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MIC59P50

General Description

Micrel

MIC59P50

8-Bit Parallel-Input Protected Latched Driver

Features

The MIC59P50 parallel-input latched driver is a high-voltage

(80V), high-current (500mA) integrated circuit comprised of

eight CMOS data latches, a bipolar Darlington transistor

driver for each latch, and CMOS control circuitry for the

common CLEAR, STROBE, and OUTPUT ENABLE func-

tions. Similar to the MIC5801, additional protection circuitry

supplied on this device includes thermal shutdown, under

voltage lockout (UVLO), and over-current shutdown.

The bipolar/MOS combination provides an extremely low-

power latch with maximum interface flexibility. The MIC59P50

has open-collector outputs capable of sinking 500mA and

integral diodes for inductive load transient suppression with

a minimum output breakdown voltage rating of 80V above V EE

(50V sustaining). The drivers can be operated with a split

supply, where the negative supply is down to –20V and may

4.4 MHz Minimum Data Input Rate

High-Voltage, High-Current Outputs

Per-Output Over-Current Shutdown (500mA Typical)

Undervoltage Lockout

Thermal Shutdown

Output Fault Flag

Output Transient Protection Diodes

CMOS, PMOS, NMOS, and TTL Compatible Inputs

Internal Pull-Down Resistors

Low-Power CMOS Latches

Single or Split Supply Operation

be paralleled for higher load current capability.

With a 5V logic supply, the MIC59P50 will typically operate at

Ordering Information

better than 5MHz. With a 12V logic supply, significantly

higher speeds are obtained. The CMOS inputs are compat-

ible with standard CMOS, PMOS, and NMOS circuits. TTL

circuits may require pull-up resistors.

Each of these eight outputs has an independent over-current

shutdown at 500 mA. Upon current shutdown, the affected

channel will turn OFF and the flag will go low until V DD is

Part Number

MIC59P50BN

MIC59P50BV

MIC59P50BWM

* 300-mil “skinny DIP”

Temperature Range

–40 ° C to +85 ° C

Package

24-Pin Plastic DIP*

28-Pin PLCC

24-Pin Wide SOIC

cycled or the ENABLE/RESET pin is pulsed high. Current

pulses less than 2 μ s will not activate over-current shutdown.

Temperatures above 165 ° C will shut down the device and

activate the open collector FLAG output at pin 1. The UVLO

circuit disables the outputs at low V DD ; hysteresis of 0.5V is

provided.

Functional Diagram

Pin Configuration

(DIP and SOIC)

STROBE

CLEAR FLAG ENABLE/RESET

ISHUTDOWN

FLAG

ILIMIT

THERMAL

24 VSS

V DD

–

IREF

IOUT / N

CLEAR

SHUTDOWN

23 OUTPUT

ENABLE/RESET

2.2R

1.25V

–

UVLO

THERMAL

SHUTDOWN

COMMON

OUTPUT

STROBE

IN 1

IN 2

22 VDD

21 OUT 1

20 OUT 2

IN 3

19 OUT 3

70k

IN 4

IN 5

18 OUT 4

17 OUT 5

Circuitry below dashed line is

included in each of the 8 channels.

IN 6

16 OUT 6

V EE

IN 7 10

IN 8 11

15 OUT 7

14 OUT 8

7-58

VEE 12

UVLO

13 COMMON

October 1998

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